- Knowledge of the ARM architecture
- Knowledge of Cadence Tensilica cores
- Design knowledge of the industry standard bus interfaces such as AMBA AXI protocol
- Worked with leading-edge technologies 5 nm or smaller.
- Knowlege of GIT repositories
- Bachelor's degree in Electrical Engineering, Computer Engineering, or related degree required.
- 8+ years of experience in hardware design
- 7+ years expertise in Digital Design including microarchitecture specification development, RTL coding in Verilog/System Verilog and Clock Domain Crossing (CDC)/LINT closure.
location: Redmond, Washington
job type: Contract
salary: $49.95 - 59.95 per hour
work hours: 8am to 5pm
education: Bachelors
responsibilities:
- Responsible for various integration tasks at the block level
- Responsible for various integration tasks at the sub-system level
- Responsible for generation of cores (Cadence Tensilica)
- Responsible for the generation and integration of NOCs (Synopsys and Arteris)
- Manage repos for shared collateral across design teams
qualifications:
- Experience level: Experienced
- Minimum 8 years of experience
- Education: Bachelors
skills:
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Pay offered to a successful candidate will be based on several factors including the candidate's education, work experience, work location, specific job duties, certifications, etc. In addition, Randstad Digital offers a comprehensive benefits package, including health, an incentive and recognition program, and 401K contribution (all benefits are based on eligibility).
This posting is open for thirty (30) days.
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